The present invention relates to semiconductor memory devices and methods for fabricating the same. More particularly, the present invention relates to structures for memory cells that include high-xcexa films or ferroelectric films.
Recently, embedded-DRAM processes for combining DRAMs with high-performance logic circuits have been put into practical use in multimedia applications requiring large memory capacity and high data transmission speed.
To form the capacitive insulating films for capacitors that serve as memory capacitors, DRAM processes to date, however, require a high-temperature heating process. Thus, a drawback of these processes to date have been that the impurities in the doped layers of the transistors included in the high-performance logic circuit have an undesirable concentration profile. Moreover, in downsizing the memory-cell transistors in DRAM, FeRAM, and like processes that use a single memory, high-temperature heating processes are preferably avoided as completely as possible.
Avoiding high-temperature heating processes requires developing MIM (Metal-Insulator-Metal) capacitors using high-xcexa films which can be formed at low temperature and which enable downsizing of the memory cells. As the high-xcexa films, perovskite-structured BST ((BaSr)TiO3) films and like dielectric films are used. Meanwhile, Pt, which has high oxidation resistance, is generally expected to hold promise as a material used for the metal electrodes in MIM capacitors. Also, as ferroelectric films, perovskite-structured SBT (SrBi2Ta2O9) films, BTO (Bi4Ti3O12) films, and like dielectric films are often used.
MIM capacitors serving as memory capacitors have, however, had the following problems to date.
First, when contact holes that are in contact with Pt-electrodes (upper electrodes) provided on the capacitive insulating film are formed, the characteristics of the capacitor may be adversely affected by, for example, the reducing atmosphere under which the contact plugs are formed. This is because a deficiency of oxygen may arise in the dielectric film due to the reducing atmosphere, since the dielectric film is generally made of an oxide. If the capacitive insulating film is a high-xcexa film or a ferroelectric film, there is an especially strong likelihood that oxygen deficiency will occur. In particular, in dielectric films having a perovskite structure, the characteristics deteriorate markedly due to oxygen deficiency.
Likewise, in devices such as DRAMs, which conventionally do not use Pt-electrodes, manufacturing process steps, such as forming the contacts, for Pt-electrodes, which are novel materials, are difficult to perform with existing equipment used for other process steps, making it necessary to run special facilities. Specifically, in a situation in which a contact hole reaching to a Pt electrode is formed in an interlayer dielectric film, for example, Pt will be sputtered from the exposed Pt-electrode, and therefore the Pt will be adhered to, e.g., walls of the chamber or components within the chamber. If the chamber is used as it is, the Pt may invade active regions in the transistors, adversely affecting the transistors"" operation.
An object of the present invention is to provide a semiconductor memory device with an MIM capacitor having excellent characteristics and a method for fabricating the same by providing a means for forming an interconnect layer which is not in direct contact with, i.e., is indirectly connected to, an upper electrode made of, for example, Pt on an capacitive insulating film.
Another object of the present invention is to provide a semiconductor memory device that requires no special equipment and, therefore, can be fabricated at low cost and a method for fabricating the same.
An inventive semiconductor memory device includes: a memory capacitor, which is formed on an insulating layer over a semiconductor substrate and includes a lower electrode, an upper electrode, and a capacitive insulating film sandwiched between the lower electrode and the upper electrode; an extension of the upper electrode and an extension of the capacitive insulating film extending respectively from the upper electrode and the capacitive insulating film of the memory capacitor; a dummy conductor member formed to be partly located under the upper-electrode extension and the capacitive insulating film extension; a conductor sidewall formed on side faces of the upper-electrode extension and the capacitive-insulating-film extension and connected to the dummy conductor member; and an upper interconnect electrically connected to the dummy conductor member.
According to this structure, the upper interconnect is not necessarily directly connected to the upper electrode. Thus, even if the upper electrode is made of a Pt film, for example, it is possible to prevent deterioration in characteristics of the capacitive insulating film resulting from exposure of the capacitive insulating film to the reducing atmosphere.
The conductor sidewall may cover the side faces of the upper-electrode extension and the capacitive-insulating-film extension to surround the entire circumference of films that include the upper electrode and extension thereof, and the capacitive insulating film and extension thereof, respectively. Then, it is ensured that the reducing atmosphere is prevented from invading the capacitive insulating film.
It is preferable that the dummy conductor member is a dummy lower electrode, the dummy lower electrode and the lower electrode being made from an identical conductor film; and the conductor sidewall electrically connects the upper-electrode extension to the dummy lower electrode.
The device may include: a bit line formed under the memory capacitor with the insulating layer sandwiched between the bit line and the memory capacitor; a local interconnect, the local interconnect and the bit line being made from an identical conductor film; and a conductor plug formed through the insulating layer to connect the dummy lower electrode to the local interconnect. Then, a structure suitable for a memory with a xe2x80x9ccapacitor over bit-linexe2x80x9d construction can be obtained utilizing the conductor film for the bit line.
The device may include: an isolating insulating film formed in the semiconductor substrate under the insulating layer; a memory cell transistor formed in a region of the semiconductor substrate surrounded by the isolating insulating film, the memory cell transistor including a gate electrode and doped layers defined within the semiconductor substrate below the gate electrode to horizontally sandwich the gate electrode therebetween; a local interconnect formed on the isolating insulating film, the local interconnect and the gate electrode being made from an identical conductor film; and a conductor plug formed through the interlevel insulating film to be connected to the local interconnect. Then, a structure suitable for both memories with xe2x80x9ccapacitor over bit-linexe2x80x9d and xe2x80x9ccapacitor under bit-linexe2x80x9d constructions can be obtained utilizing the conductor film (e.g., a polysilicon film) for the gate electrode.
The device may include: a memory cell transistor formed in a region of the semiconductor substrate, the memory cell transistor including a gate electrode and doped layers defined within the semiconductor substrate below the gate electrode to horizontally sandwich the gate electrode therebetween; a local interconnect made of another doped layer to be separated from the doped layers defined within the semiconductor substrate; and a conductor plug formed through the insulating film and connected to the local interconnect. Then, a structure suitable for both memories with xe2x80x9ccapacitor over bit-linexe2x80x9d and xe2x80x9ccapacitor under bit-linexe2x80x9d constructions can be obtained utilizing a process for forming source/drain regions.
The dummy conductor member may be a local interconnect made of a conductor film filling in a trench that is formed in the insulating layer. Then, a structure suitable for both memories with xe2x80x9ccapacitor over bit-linexe2x80x9d and xe2x80x9ccapacitor under bit-linexe2x80x9d constructions can be obtained.
The dummy conductor member may be a dummy lower electrode, the dummy conductor member and the lower electrode being made from an identical conductor film; the conductor sidewall may be in contact with the upper-electrode extension and the dummy lower electrode; and the upper interconnect may be in contact with the dummy lower electrode. Then, a relatively simple structure suitable for both memories with xe2x80x9ccapacitor over bit-linexe2x80x9d and xe2x80x9ccapacitor under bit-linexe2x80x9d constructions can be obtained.
The lower electrode, the capacitive insulating film and the upper electrode of the memory capacitor may be cylindrical. Then, a semiconductor memory device in which memory cells are relatively densely arranged is implemented.
An inventive method for fabricating a semiconductor memory device, which includes a memory capacitor and an upper interconnect, the memory capacitor including a lower electrode, an upper electrode and a capacitive insulating film sandwiched between the lower and upper electrodes, the upper interconnect being electrically connected to the upper electrode of the memory capacitor, includes the steps of: a) forming a first conductor film on an insulating layer over a semiconductor substrate, and then patterning the first conductor film to form the lower electrode and a film for a dummy lower electrode in mutually separated positions; b) forming a dielectric film covering the lower electrode and the dummy film; c) forming a second conductor film covering the dielectric film; d) forming, over the second conductor film, an etching mask covering the whole of the lower electrode and part of the dummy film; e) patterning the second conductor film, the dielectric film and the dummy film, thereby forming the capacitive insulating film and an extension of the capacitive insulating film from the dielectric film, forming the upper electrode and an extension of the upper electrode from the second conductor film, and forming a dummy lower electrode from the dummy film; and f) depositing a third conductor film over a substrate and then anisotropically etching back the third conductor film, thereby forming a conductor sidewall covering exposed parts of respective side faces of the second conductor film, the dielectric film and the dummy lower electrode, after the step e) has been performed.
According to this method, in the step a), a dummy lower electrode is formed concurrently with the formation of a lower electrode for a memory capacitor, and then the lower electrode and the dummy lower electrode are connected to each other via a conductor sidewall in the step f). In addition, it is unnecessary to increase the number of photolithographic process steps between the steps of a) and f).
In the step d), a hard mask may be formed as the etching mask. Then, accuracy in patterning can be improved in the step e).
The method may include, before the step a) is performed, the steps of: forming an insulating film for forming steps therein on the insulating layer; and forming, in the insulating film for forming steps, a first opening in which the memory capacitor is to be formed, and a second opening in which the dummy lower electrode is to be formed. In this method, in the step a), the lower electrode may be formed on the side and the bottom of the first opening, and the dummy lower electrode may be formed on the side and the bottom of the second opening. In the step d), the etching mask may be formed to cover only part of the second opening. Then, a semiconductor memory device in which memory cells are relatively densely arranged is implemented.